Project 3 - Sequential Logic
In this part of the course you will have to read chapter 3 of the book (Sequential Logic), after reading the chapter you will have to read the following instructions to be able to implement project 2.
Instructions
Each chip in this project is specified by a skeletal *.hdl program with a missing implementation part. In addition, each chip is accompanied by a supplied *.tst script file that tells the hardware simulator how to test it, and a supplied *.cmp file that lists the expected output of the *.hdl program, as mandated by the *.tst script file. All these files are available in a single Chips Set zip file, which you should download to your computer (explained below).
The contract: when loaded into the hardware simulator, your chip design (*.hdl program modified by you), tested on the script specified in the supplied *.tst file, should deliver the behavior specified in the supplied *.cmp file. If that is not the case, the simulator will let you know.
Build the following gates, using solely previously-built gates.
1-bit
register. 16-bit
register. 8-register
RAM. 64-register
RAM. 512-register
RAM. 4K-register
RAM. 16K-register
RAM. 16-bit
counter.
Chip(HDL)
Function
Test
Scripts
Compare
Files
Please submit the files in 2 directories called 1 and 2 :
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In directroy 1 you'll have to put the following chips (Bit,Register,RAM8,RAM64,PC).
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In directory 2 you'll have to put the following chips (RAM512,RAM4K,RAM16K).
Resources
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Chips Set (project3.zip) (download): Extract to an empty directory, and keep the default directory structure as is.
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Chapter 3 of the book - "Sequential Logic".
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Appendix A - HDL.
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Appendix B - Test Script Language.
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Guidelines for submitting.
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Submission is done through the Administratives page.