Project
1 - Boolean Logic
In this part of the course you will have to read chapter 1 of the book (Boolean Logic), after reading the chapter you will have to read the following instructions to be able to implement project 1.
Instructions
Each chip in this project is specified by a skeletal *.hdl program with a missing implementation part. In addition, each chip is accompanied by a supplied *.tst script file that tells the hardware simulator how to test it, and a supplied *.cmp file that lists the expected output of the *.hdl program, as mandated by the *.tst script file. All these files are available in a single Chips Set zip file, which you should download to your computer (explained below).
The contract: when loaded into the hardware simulator, your chip design (*.hdl program modified by you), tested on the script specified in the supplied *.tst file, should deliver the behavior specified in the supplied *.cmp file. If that is not the case, the simulator will let you know.
Build the following gates, using solely elementary NAND gates and previously-built gates.
Not
gate And
gate Or
gate Xor
gate 16-bit
not gate 16-bit
and gate 16-bit
or gate Or(in0,in1,...,in7)
gate 1-bit
multiplexor 16-bit
/ 2-inputs multiplexor 16-bit
/ 4-inputs multiplexor 16-bit
/ 8-inputs multiplexor 1-bit
demultiplexor 4-outputs
demultiplexor 8-outputs
demultiplexor
Chip(HDL)
Function
Test
scripts
If you cannot complete the construction of one or more of these gates, there is no need to panic. The hardware simulator contains executable versions of all the above chips. Hence, lack of HDL versions of one chip or another do not delay the construction of more advanced chips that rely on them. Specifically, if the simulator fails to find a chipName.hdl file in your working directory, it invokes a chipName.java class instead. This class has the same interface and functionality as the missing chipName.hdl program.
Resources
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Chips Set (download): Extract to an empty directory, and keep the default directory structure as is.
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Chapter 1 of the book - "Boolean Logic".
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Appendix A - HDL.
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Appendix B - Test Script Language.
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Guidelines for submitting.
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Submission is done through the Administratives page.